Sure, no argument there. For Google, producing and using TPUs, is probably cheaper than buying nvidia hardware.
The interconnect hardware is present on the dgx-1 board. The point of my previous comment is that it doesn't make sense to compare an entire TPU module (containing 4x TPUs) to a V100 board. The closest comparison to a…
A single V100 board is vastly smaller than a TPU module with 4 TPU chips. The closest comparison in terms of size would be 1 Volta DGX-1 (8x V100s) compared to 2 TPU modules (8x TPU2 chips). Volta DGX-1:…
A single chip is only 45 TFLOPS. It is 180 TFLOPs per module (4x TPU chips): https://arstechnica.com/information-technology/2017/05/googl...
Google's 180 teraflop number is for a module, which contains 4 TPU chips. Meaning each TPU is 45 teraflops. See: https://arstechnica.com/information-technology/2017/05/googl...
It is actually 45 teraflops per TPU2 chip and 180 teraflops for a module (4x chips): https://arstechnica.com/information-technology/2017/05/googl... V100 is 120 teraflops of tensor ops per chip:…
Sure, no argument there. For Google, producing and using TPUs, is probably cheaper than buying nvidia hardware.
The interconnect hardware is present on the dgx-1 board. The point of my previous comment is that it doesn't make sense to compare an entire TPU module (containing 4x TPUs) to a V100 board. The closest comparison to a…
A single V100 board is vastly smaller than a TPU module with 4 TPU chips. The closest comparison in terms of size would be 1 Volta DGX-1 (8x V100s) compared to 2 TPU modules (8x TPU2 chips). Volta DGX-1:…
A single V100 board is vastly smaller than a TPU module with 4 TPU chips. The closest comparison in terms of size would be 1 Volta DGX-1 (8x V100s) compared to 2 TPU modules (8x TPU2 chips). Volta DGX-1:…
A single chip is only 45 TFLOPS. It is 180 TFLOPs per module (4x TPU chips): https://arstechnica.com/information-technology/2017/05/googl...
Google's 180 teraflop number is for a module, which contains 4 TPU chips. Meaning each TPU is 45 teraflops. See: https://arstechnica.com/information-technology/2017/05/googl...
It is actually 45 teraflops per TPU2 chip and 180 teraflops for a module (4x chips): https://arstechnica.com/information-technology/2017/05/googl... V100 is 120 teraflops of tensor ops per chip:…