A few reasons why EDIF might not be a good candidate for this: 1) The standards body that controls EDIF no longer exists, this could limit the ability to evolve and improve it. 2) Large placed and routed FPGA designs…
A few reasons why EDIF might not be a good candidate for this: 1) The standards body that controls EDIF no longer exists, this could limit the ability to evolve and improve it. 2) Large placed and routed FPGA designs…