Records are really great in theory but I have usually found difficult in practice. Mixing them with Verilog or SystemVerilog sometimes is not possible or requires a wrapper of sorts. And then of course tool support…
If you're not looking to implement one totally from scratch, this could be a good start: http://llvm.org/docs/tutorial/
Records are really great in theory but I have usually found difficult in practice. Mixing them with Verilog or SystemVerilog sometimes is not possible or requires a wrapper of sorts. And then of course tool support…
If you're not looking to implement one totally from scratch, this could be a good start: http://llvm.org/docs/tutorial/