There are tools for formal verification of design input, and they are being used, but not for everything. Why there are still errata for silicon 1. Writing a formal specification of your intended behavior is hard and…
Would be really nice honestly. But I don't think it will be coming anytime soon, it's just too expensive to build a chip. The one-time costs for masks are just much more expensive as for PCBs, so wafer shuttle services…
But if it's a pointer, the compiler doesn't know the alignment at compile time. Should the compiler insert an alignment check of every pointer access?
> Meanwhile, the actual computers we have been using for decades have no problems actually just loading 4 bytes through any arbitrary pointer with zero overhead. But no. Not if those 4 bytes span a cacheline boundary,…
There are tools for formal verification of design input, and they are being used, but not for everything. Why there are still errata for silicon 1. Writing a formal specification of your intended behavior is hard and…
Would be really nice honestly. But I don't think it will be coming anytime soon, it's just too expensive to build a chip. The one-time costs for masks are just much more expensive as for PCBs, so wafer shuttle services…
But if it's a pointer, the compiler doesn't know the alignment at compile time. Should the compiler insert an alignment check of every pointer access?
> Meanwhile, the actual computers we have been using for decades have no problems actually just loading 4 bytes through any arbitrary pointer with zero overhead. But no. Not if those 4 bytes span a cacheline boundary,…