Ask me about GCs :)
The MIPS-I chip also had load delay slots along with branch delay slots.
An aside but "Making Money" by Terry Pratchett references a similar sub-office of the Post Office in Ankh-Morpork--the Blind Letter Office. Amusingly, Lord Vetinari is able to assist with some as their addresses are…
The Evening Standard (https://www.standard.co.uk/news/uk/rwanda-asylum-deal-uk-asy...) quotes 200 people from the Rwandan Government, "but that it could be scaled up". A research briefing document from the House Of…
rescue.org (https://www.rescue.org/uk/article/why-uk-government-should-r... section 5) reports GBP 140m so far, GBP 120m on up front costs along with The Times reporting a further payment of GBP 20m. The Migration…
'signed' and 'unsigned' on their own--act as short-hand for 'signed int' and 'unsigned int' in C and C++. Note that the size of an 'int' is dependant on the "data model"[1]. As for whether it's the most optimal is far…
> This is a great overview. I don't remember having to put in padding instructions to prevent the pipeline issues mentioned here; maybe we just never ran into that. (I wrote pretty much all the R3000 code for Crash 1…
Indeed, the likes of x86 little endian assumptions of programmers (even compiler engineers) can be hilarious (in the sad clown way) when targeting something like MIPS64 big endian.
> There is no legal reason why ministers cannot reject Brexit; There is, for a revocation of article 50 notice to be legal, Parliament has to pass a motion directing the Government to do so[1]. [1]…
Nit: It's Parliament cannot bind a future Parliament rather than UK governments cannot bind future UK governments. https://www.parliament.uk/about/how/role/sovereignty The subtly here is that usually a government…
MIPS has what's called an Application Specific Extension (ASE) basis for extending a given MIPS core for particular areas. The MIPS DSP ASE extends the base instruction set with certain instructions applicable to…
It would be more likely that nanoMIPS would be considered for open sourcing if that the implementation was to be made open source. Otherwise it would be the fobbing off of releasing the code to the InterAptiv which has…
MIPSR6 does away with the HI/LO registers and have multiplication instructions which return the result to GPR registers. Pre-R6 MIPS cores have the MUL instruction which hide the usage of the HI/LO registers, but do…
nanoMIPS doesn't have delay slots IIRC. microMIPSR6 also deprecated delay slots for branches. MIPSR6 got rid of delay slots for a family of branches called 'compact branches' which have 'forbidden slots' which require…
GC write barriers are implemented by expanding sequences that update pointers to perform some sort of additional action. Their purpose is to capture some information about the updated pointer that the GC can then use to…
Almost every modern compiler uses some form of intermediate representation. The choice of IR is shaped by history and design. As the posted article shows, LLVM uses a SSA based IR to describe programs. GCC in contrast…
> It's pretty cool that clang uses this when it knows the value in the first argument is byte-sized. Clang is using the 8 bit subregister due to how it legalizes types. When LLVM-IR is compiled for a target, it…
An aside: Tolpin and Toft designed an extension to the functional language ML which used region based memory managed instead of traditional garbage collection for ML. This lifted the lifetimes of variables into ML's…
> At the time Intel had already introduced some mobile silicon, but there was little uptake. So they were iterating; they wanted to improve for each succeeding generation. But they had a kind of design-by-committee…
My old Q6600 could do this to a degree. Sometimes the fan wouldn't spin up on boot, so there was just passive cooling. i'd try playing a game/doing something and performance would start digging it's way to China. At…
I've dealt with bugs that existed at -O0, -O2 was fine. But the bug was in the compiler itself.
One option in GCC I'm aware of is -faggressive-loop-optimizations . Quoting the manual "This option tells the loop optimizer to use language constraints to derive bounds for the number of iterations of a loop. This…
As I know, some of those contributors are just making systemic changes throughout LLVM, which would require touching the PowerPC backend. I'm not at all surprised at the @[a-z.]+.ibm.com contributors, the @anl.gov is…
The NSA are doing this now? I was friends with someone in TCD (Ireland) who did this work >3 years ago.
That video was amazing, thank you.
> I absolutely prefer strict typing myself. The issue becomes whether or not one thinks type coercion should be a thing. As a strong typing fanatic, I'd rather have the interpreter/compiler scream at me. In my opinion…
The MIPS-I chip also had load delay slots along with branch delay slots.
An aside but "Making Money" by Terry Pratchett references a similar sub-office of the Post Office in Ankh-Morpork--the Blind Letter Office. Amusingly, Lord Vetinari is able to assist with some as their addresses are…
The Evening Standard (https://www.standard.co.uk/news/uk/rwanda-asylum-deal-uk-asy...) quotes 200 people from the Rwandan Government, "but that it could be scaled up". A research briefing document from the House Of…
rescue.org (https://www.rescue.org/uk/article/why-uk-government-should-r... section 5) reports GBP 140m so far, GBP 120m on up front costs along with The Times reporting a further payment of GBP 20m. The Migration…
'signed' and 'unsigned' on their own--act as short-hand for 'signed int' and 'unsigned int' in C and C++. Note that the size of an 'int' is dependant on the "data model"[1]. As for whether it's the most optimal is far…
> This is a great overview. I don't remember having to put in padding instructions to prevent the pipeline issues mentioned here; maybe we just never ran into that. (I wrote pretty much all the R3000 code for Crash 1…
Indeed, the likes of x86 little endian assumptions of programmers (even compiler engineers) can be hilarious (in the sad clown way) when targeting something like MIPS64 big endian.
> There is no legal reason why ministers cannot reject Brexit; There is, for a revocation of article 50 notice to be legal, Parliament has to pass a motion directing the Government to do so[1]. [1]…
Nit: It's Parliament cannot bind a future Parliament rather than UK governments cannot bind future UK governments. https://www.parliament.uk/about/how/role/sovereignty The subtly here is that usually a government…
MIPS has what's called an Application Specific Extension (ASE) basis for extending a given MIPS core for particular areas. The MIPS DSP ASE extends the base instruction set with certain instructions applicable to…
It would be more likely that nanoMIPS would be considered for open sourcing if that the implementation was to be made open source. Otherwise it would be the fobbing off of releasing the code to the InterAptiv which has…
MIPSR6 does away with the HI/LO registers and have multiplication instructions which return the result to GPR registers. Pre-R6 MIPS cores have the MUL instruction which hide the usage of the HI/LO registers, but do…
nanoMIPS doesn't have delay slots IIRC. microMIPSR6 also deprecated delay slots for branches. MIPSR6 got rid of delay slots for a family of branches called 'compact branches' which have 'forbidden slots' which require…
GC write barriers are implemented by expanding sequences that update pointers to perform some sort of additional action. Their purpose is to capture some information about the updated pointer that the GC can then use to…
Almost every modern compiler uses some form of intermediate representation. The choice of IR is shaped by history and design. As the posted article shows, LLVM uses a SSA based IR to describe programs. GCC in contrast…
> It's pretty cool that clang uses this when it knows the value in the first argument is byte-sized. Clang is using the 8 bit subregister due to how it legalizes types. When LLVM-IR is compiled for a target, it…
An aside: Tolpin and Toft designed an extension to the functional language ML which used region based memory managed instead of traditional garbage collection for ML. This lifted the lifetimes of variables into ML's…
> At the time Intel had already introduced some mobile silicon, but there was little uptake. So they were iterating; they wanted to improve for each succeeding generation. But they had a kind of design-by-committee…
My old Q6600 could do this to a degree. Sometimes the fan wouldn't spin up on boot, so there was just passive cooling. i'd try playing a game/doing something and performance would start digging it's way to China. At…
I've dealt with bugs that existed at -O0, -O2 was fine. But the bug was in the compiler itself.
One option in GCC I'm aware of is -faggressive-loop-optimizations . Quoting the manual "This option tells the loop optimizer to use language constraints to derive bounds for the number of iterations of a loop. This…
As I know, some of those contributors are just making systemic changes throughout LLVM, which would require touching the PowerPC backend. I'm not at all surprised at the @[a-z.]+.ibm.com contributors, the @anl.gov is…
The NSA are doing this now? I was friends with someone in TCD (Ireland) who did this work >3 years ago.
That video was amazing, thank you.
> I absolutely prefer strict typing myself. The issue becomes whether or not one thinks type coercion should be a thing. As a strong typing fanatic, I'd rather have the interpreter/compiler scream at me. In my opinion…