From my professional experience of programming and debugging networking equipment, this could be a switch/router with a buffer with bad memory (stuck bit maybe). The better chips have CRC/Parity/ECC to cover such issues…
After more consideration it is much more likely to be LPDDR4X just like the recently released A14 chip. It would seem unlikely that they would have developed a brand new memory interface.
My guess is that they are using up to 2 HBM2 memory stacks (from the picture). Each is limited to 8GB . If they were to go to HBM2e in M2 they could get up to 2x24GB. The biggest advantage of HBM is lower power per bit…
Flex Ethernet is that attempt to standardize the lane stripping at whatever speed. Unfortunately that effort has grown to incorporate a kitchen sink worth of other features like groups and shaping... Which raises the…
The pirates are a spoof of another french Belgian comic named Redbeard (Barbe Rouge) https://en.wikipedia.org/wiki/Redbeard_(comics) The wikipedia page even has the Asterix parodies next to the actual ones. Not that it…
As one of the authors of the original paper the data is based on I have fond memories as a graduate student of standardizing the performance data to SpecInt which did not exist till the 2000s. So for the older…
If you want to build a non-blocking Clos network of 2N ports with switches with N ports you need to take 4 switches in the front with N/2 ports and 2 switches in the back interconnecting all the ports to the back for a…
Tons of problems with costs... 1) Copper cables only go to 7m because attenuation is too high after 7m to recover signals at 10G/25G lanes, get ready for lower length with 50G PAM4 2) Transceivers are free... no they…
What is really missing here is that you can build modular switches out of multiple chips that are a lot more cost effective than connecting single chip boxes mostly because the internal links in a modular chassis in…
The real debate is between OSPF and QSFP-DD as they are the only ones with a shot at high density. QSFP-DD is backwards compatible so that you can run your 400G port as a 100G or 40G with 4 lanes at 25G/10G. OSFP will…
Hopefully you guys have ECC on your 64MB of SRAM, otherwise the meant time to bit flip due to Single Event Upset (SEU) is around 400 days ( based on 200 Fit/Mb/Billion Hours from previous experience ).
Like you said the host might have small buffers and without Pause it would drop, but who's supposed to buffer the packets, the cheap switch with 16kB of buffers and super idiotic buffer configuration such that everyone…
Some datacenters enable Priority Flow Control (PFC) which is different in that it pauses only the traffic with a specific PCP ( Priority in 802.1Q vlan tag ). They assign storage traffic a specific vlan priority and…
Ah... The problems of crappy consumer ethernet equipment ( I work at an ethernet switch vendor so excuse the rant ) What is likely happening is that your switch is configured by default to implement both rx and tx…
What nobody talks about is the very good reason why employers give only 90 days after leaving a company to exercise options is that there is also a tax liability to the company for an employee exercising an option.…
In the networking world Fulcrum built some very low latency switch chips used in switch routers using asynchronous logic. The Alta switch chip was the last of that generation.…
Also note Spotify published their own stuff also on Arista hardware https://labs.spotify.com/2016/01/26/sdn-internet-router-part... Podcast where David Barroso talks about it:…
From my professional experience of programming and debugging networking equipment, this could be a switch/router with a buffer with bad memory (stuck bit maybe). The better chips have CRC/Parity/ECC to cover such issues…
After more consideration it is much more likely to be LPDDR4X just like the recently released A14 chip. It would seem unlikely that they would have developed a brand new memory interface.
My guess is that they are using up to 2 HBM2 memory stacks (from the picture). Each is limited to 8GB . If they were to go to HBM2e in M2 they could get up to 2x24GB. The biggest advantage of HBM is lower power per bit…
Flex Ethernet is that attempt to standardize the lane stripping at whatever speed. Unfortunately that effort has grown to incorporate a kitchen sink worth of other features like groups and shaping... Which raises the…
The pirates are a spoof of another french Belgian comic named Redbeard (Barbe Rouge) https://en.wikipedia.org/wiki/Redbeard_(comics) The wikipedia page even has the Asterix parodies next to the actual ones. Not that it…
As one of the authors of the original paper the data is based on I have fond memories as a graduate student of standardizing the performance data to SpecInt which did not exist till the 2000s. So for the older…
If you want to build a non-blocking Clos network of 2N ports with switches with N ports you need to take 4 switches in the front with N/2 ports and 2 switches in the back interconnecting all the ports to the back for a…
Tons of problems with costs... 1) Copper cables only go to 7m because attenuation is too high after 7m to recover signals at 10G/25G lanes, get ready for lower length with 50G PAM4 2) Transceivers are free... no they…
What is really missing here is that you can build modular switches out of multiple chips that are a lot more cost effective than connecting single chip boxes mostly because the internal links in a modular chassis in…
The real debate is between OSPF and QSFP-DD as they are the only ones with a shot at high density. QSFP-DD is backwards compatible so that you can run your 400G port as a 100G or 40G with 4 lanes at 25G/10G. OSFP will…
Hopefully you guys have ECC on your 64MB of SRAM, otherwise the meant time to bit flip due to Single Event Upset (SEU) is around 400 days ( based on 200 Fit/Mb/Billion Hours from previous experience ).
Like you said the host might have small buffers and without Pause it would drop, but who's supposed to buffer the packets, the cheap switch with 16kB of buffers and super idiotic buffer configuration such that everyone…
Some datacenters enable Priority Flow Control (PFC) which is different in that it pauses only the traffic with a specific PCP ( Priority in 802.1Q vlan tag ). They assign storage traffic a specific vlan priority and…
Ah... The problems of crappy consumer ethernet equipment ( I work at an ethernet switch vendor so excuse the rant ) What is likely happening is that your switch is configured by default to implement both rx and tx…
What nobody talks about is the very good reason why employers give only 90 days after leaving a company to exercise options is that there is also a tax liability to the company for an employee exercising an option.…
In the networking world Fulcrum built some very low latency switch chips used in switch routers using asynchronous logic. The Alta switch chip was the last of that generation.…
Also note Spotify published their own stuff also on Arista hardware https://labs.spotify.com/2016/01/26/sdn-internet-router-part... Podcast where David Barroso talks about it:…