I use both vendors' toolsets, have found occasional bugs in both, have my regrets, but all-in-all they are quite comparable, and quite remarkable for what they enable. In both tools most of my design spins take <3…
Xilinx didn't choose anything, rather they simply linked to a blog (mine). These cores are more austere, smaller, simpler than MicroBlaze. http://www.fpgacpu.org/log/sep00.html#000919
"how much better" -- I didn't understand, sorry. Even with 18 years of x86 performance advances, it takes much longer to PAR the large FPGAs now than it did back in the day.
With the Xilinx ISE toolset I am currently using (which Xilinx is deprecating in favor of the new Vivado toolset) it parallelizes/multithreads poorly. I understand that the place and route algorithm is based upon…
Hi, Jan here. pdq, the last time I built this design, with more fully elaborated processors (control units + multiplier FUs) it took three hours and 16 GB physical RAM on a Core i7-4960HQ rMBP.
I use both vendors' toolsets, have found occasional bugs in both, have my regrets, but all-in-all they are quite comparable, and quite remarkable for what they enable. In both tools most of my design spins take <3…
Xilinx didn't choose anything, rather they simply linked to a blog (mine). These cores are more austere, smaller, simpler than MicroBlaze. http://www.fpgacpu.org/log/sep00.html#000919
"how much better" -- I didn't understand, sorry. Even with 18 years of x86 performance advances, it takes much longer to PAR the large FPGAs now than it did back in the day.
With the Xilinx ISE toolset I am currently using (which Xilinx is deprecating in favor of the new Vivado toolset) it parallelizes/multithreads poorly. I understand that the place and route algorithm is based upon…
Hi, Jan here. pdq, the last time I built this design, with more fully elaborated processors (control units + multiplier FUs) it took three hours and 16 GB physical RAM on a Core i7-4960HQ rMBP.