http://gallium.inria.fr/blog/intel-skylake-bug/ another great blogpost on the topic
I'm not really qualified to explain why such a layout was chosen, my understanding of ocaml internal is limited. The header layout is described here : https://github.com/ocaml/ocaml/blob/4.04.2/byterun/caml/mlva... I…
We pondered reporting this directly to GCC too so that they can implement a workaround. But despite the buzz generated by this issue in the press I believe Intel is right in saying that this bug is very unlikely to…
> Additionally, what I miss in this story is which source code actually produces [...] (this instruction) The post does not indeed make it clear, but the two instructions andb $252, %ah movq %rax, (%rbx) come from the…
http://gallium.inria.fr/blog/intel-skylake-bug/ another great blogpost on the topic
I'm not really qualified to explain why such a layout was chosen, my understanding of ocaml internal is limited. The header layout is described here : https://github.com/ocaml/ocaml/blob/4.04.2/byterun/caml/mlva... I…
We pondered reporting this directly to GCC too so that they can implement a workaround. But despite the buzz generated by this issue in the press I believe Intel is right in saying that this bug is very unlikely to…
> Additionally, what I miss in this story is which source code actually produces [...] (this instruction) The post does not indeed make it clear, but the two instructions andb $252, %ah movq %rax, (%rbx) come from the…