> how does the system recover if that were to happen? The Ethereum 2.0 consensus layer gracefully falls back to a slightly biasable form of randomness called RANDAO. This is merely a "weakening" of the consensus, not a…
> If there’s a reward for computing a VDF faster than everyone else There's no direct reward for being a bit faster than everyone else. If you are much faster (say, 100x faster than the general public) then you may be…
> if it's not embarrassingly parallelizable, first, tell me why It's a cryptographic assumption that repeated squaring in an RSA group is "inherently sequential". This assumption was first made in 1996 by Rivest, Shamir…
One efficient verification scheme is by Benjamin Wesolowski (see academic paper [here](https://eprint.iacr.org/2018/623.pdf)). The scheme is surprisingly simple and fits on just one slide. See…
ELI5 version: 100 people, one by one, (re)roll dice placed in a dark room. After the last person lights turn on, revealing a fair random number. The Verifiable Delay Function (VDF) ensures lights aren't turned on early.…
The ultimate goal is indeed to build an ultra-fast ASIC. There's a $1M ASIC circuit competition planned for for 2020. This $100K FPGA competition is a "warm up" to the ASIC competition. A bit more information here…
Ballpark latency numbers per 2048-bit modular multiplication: CPU—1100ns FPGA—66ns ASIC—1ns (expected) If you're a hardware engineer (or mathematician) interested is building an ultra-low latency ASIC, please email…
> how does the system recover if that were to happen? The Ethereum 2.0 consensus layer gracefully falls back to a slightly biasable form of randomness called RANDAO. This is merely a "weakening" of the consensus, not a…
> If there’s a reward for computing a VDF faster than everyone else There's no direct reward for being a bit faster than everyone else. If you are much faster (say, 100x faster than the general public) then you may be…
> if it's not embarrassingly parallelizable, first, tell me why It's a cryptographic assumption that repeated squaring in an RSA group is "inherently sequential". This assumption was first made in 1996 by Rivest, Shamir…
One efficient verification scheme is by Benjamin Wesolowski (see academic paper [here](https://eprint.iacr.org/2018/623.pdf)). The scheme is surprisingly simple and fits on just one slide. See…
ELI5 version: 100 people, one by one, (re)roll dice placed in a dark room. After the last person lights turn on, revealing a fair random number. The Verifiable Delay Function (VDF) ensures lights aren't turned on early.…
The ultimate goal is indeed to build an ultra-fast ASIC. There's a $1M ASIC circuit competition planned for for 2020. This $100K FPGA competition is a "warm up" to the ASIC competition. A bit more information here…
Ballpark latency numbers per 2048-bit modular multiplication: CPU—1100ns FPGA—66ns ASIC—1ns (expected) If you're a hardware engineer (or mathematician) interested is building an ultra-low latency ASIC, please email…