So don't wait. Tarballs already available for testing[1] and an example using esp-idf.[2] [1]: https://github.com/kassane/zig-espressif-bootstrap/releases [2]: https://github.com/kassane/zig-esp-idf-sample
Unfortunately, the upstream zig toolchain (LLVM codegen) does not support the Xtensa architecture (opaque CPU features), but it is possible to use riscv32 for esp32 from the C2/C3/C6, H2 and the new P4 release. I'm…
There are some projects trying to bring this experience. https://github.com/ibokuri/concepts https://github.com/mov-rax/zig-validate https://github.com/yrashk/zig-ctc
So don't wait. Tarballs already available for testing[1] and an example using esp-idf.[2] [1]: https://github.com/kassane/zig-espressif-bootstrap/releases [2]: https://github.com/kassane/zig-esp-idf-sample
Unfortunately, the upstream zig toolchain (LLVM codegen) does not support the Xtensa architecture (opaque CPU features), but it is possible to use riscv32 for esp32 from the C2/C3/C6, H2 and the new P4 release. I'm…
There are some projects trying to bring this experience. https://github.com/ibokuri/concepts https://github.com/mov-rax/zig-validate https://github.com/yrashk/zig-ctc