I agree. HyperTransport was stunning when it came out. Revolutionary, even. Ditto for AMD64, still the standard as we speak. I'm not sure, however, if this is due to Intel resting on their laurels vs an entire Intel…
Please write more and publish it.
Most is invalid in principle, perhaps not in practice (stupid as that is): 1. Ye shall use C11 memset_s(). 2. Ye shall (as you note) use a reallocarray() with OpenBSD-like (ANSI C) wrap checking. 3. Ye shall use…
I work on both. Intel is closing the gap with their DPDK, but Cavium creams them on clock-by-clock and on cost of goods. Cavium Octeon chips currently scale to 32 cores at 1.4Ghz, but with ZIP, GZIP, AES, SHA1, etc…
I agree. HyperTransport was stunning when it came out. Revolutionary, even. Ditto for AMD64, still the standard as we speak. I'm not sure, however, if this is due to Intel resting on their laurels vs an entire Intel…
Please write more and publish it.
Most is invalid in principle, perhaps not in practice (stupid as that is): 1. Ye shall use C11 memset_s(). 2. Ye shall (as you note) use a reallocarray() with OpenBSD-like (ANSI C) wrap checking. 3. Ye shall use…
I work on both. Intel is closing the gap with their DPDK, but Cavium creams them on clock-by-clock and on cost of goods. Cavium Octeon chips currently scale to 32 cores at 1.4Ghz, but with ZIP, GZIP, AES, SHA1, etc…