Thank you for your interest. We are planning to create a web page for this soon (likely http://swarm.mit.edu -- it's not live yet). Till then, you should be able to find our papers and some upcoming ones at my advisor,…
2: We are currently working on a compiler to automatically delineate tasks, assign domains etc. given sequential code. As part of that effort, we are looking at SPEC workloads, yes.
Your intuition on this improving Thread Level Speculation (TLS) is correct. I do want to clarify that this is not just a better implementation of TLS though -- our execution model is more expressive and avoids some of…
This is a concern orthogonal to our work. Today, there are commercial chips with a large number of cores / processing elements today, e.g. NVidia's Volta has ~5120 "cores", Intel's Xeon Phi has upto 72 cores. And there…
1. Currently the programmer needs to delineate code into tasks. A couple of points to note: -- Often the programmer can start with the serial code, and determine how to delineate tasks. In our experience this is often…
Hi all. This is Suvinay Subramanian from MIT. I am one of the authors on the Fractal paper. I wanted to provide some context for this work, and briefly summarize our paper. I hope this will address some of the comments…
The 88x is the maximum speedup we get, yes. We believe our ideas are applicable to a wide range of domains ranging from databases, to discrete-event simulation, to machine learning, and graph analytics.
This is a new execution model + hardware architecture. Currently we have evaluated it in simulation only. But stay tuned for hardware.
We use the x86-64 ISA for our cores, yes. But our ideas are applicable beyond the x86 ISA. As nn3 points out, currently our ideas are evaluated in simulation.
Correct. One of the goals of this work was to expose and exploit the abundant parallelism within large atomic tasks. However, the tasks within a domain can be ordered or unordered. Our system will exploit any kind of…
Thank you for your interest. We are planning to create a web page for this soon (likely http://swarm.mit.edu -- it's not live yet). Till then, you should be able to find our papers and some upcoming ones at my advisor,…
2: We are currently working on a compiler to automatically delineate tasks, assign domains etc. given sequential code. As part of that effort, we are looking at SPEC workloads, yes.
Your intuition on this improving Thread Level Speculation (TLS) is correct. I do want to clarify that this is not just a better implementation of TLS though -- our execution model is more expressive and avoids some of…
This is a concern orthogonal to our work. Today, there are commercial chips with a large number of cores / processing elements today, e.g. NVidia's Volta has ~5120 "cores", Intel's Xeon Phi has upto 72 cores. And there…
1. Currently the programmer needs to delineate code into tasks. A couple of points to note: -- Often the programmer can start with the serial code, and determine how to delineate tasks. In our experience this is often…
Hi all. This is Suvinay Subramanian from MIT. I am one of the authors on the Fractal paper. I wanted to provide some context for this work, and briefly summarize our paper. I hope this will address some of the comments…
The 88x is the maximum speedup we get, yes. We believe our ideas are applicable to a wide range of domains ranging from databases, to discrete-event simulation, to machine learning, and graph analytics.
This is a new execution model + hardware architecture. Currently we have evaluated it in simulation only. But stay tuned for hardware.
We use the x86-64 ISA for our cores, yes. But our ideas are applicable beyond the x86 ISA. As nn3 points out, currently our ideas are evaluated in simulation.
Correct. One of the goals of this work was to expose and exploit the abundant parallelism within large atomic tasks. However, the tasks within a domain can be ordered or unordered. Our system will exploit any kind of…