sybreon
- Karma
- 41
- Created
- July 27, 2009 (16y ago)
- Submissions
- 0
- Show HN: My hardware implementation of the DCPU-16 in Verilog RTL (sybreon.github.com)
This is a pipelined hardware implementation of the DCPU-16 cpu designed by @notch for his new game 0x10c in Verilog RTL. It is written entirely in RTL Verilog and is fully synthesisable. While basically functional,…