Is the flowchart system different from a transition system? https://en.wikipedia.org/wiki/Transition_system If not, I don't know of a way to make that machine without some timing assumptions.…
The main issue with the comments are people are mixing terms without knowing it. To many a single instruction executed on a CPU is an atomic event. This is not the case for a circuit designer (and FPGAs are closer to…
Even the most trivial design will need some form of synchronization which implies handshaking of some kind. Asynchronous design is a really interesting field where it's pretty easy to get wins at the circuit level, but…
> The same can be done with asynchronous designs, in more relaxed way. Sure, just ask these guys: https://chronostech.com/technology Chronos Link: A QDI Interconnect for Modern SoCs…
There's a lot of interesting research out there as designers having been toying with asynchronous for decades. For example this one sponsored by Intel where they put an asynchronous instruction length decoder into a…
This implies yield loss is mostly due to small delay defects and not stuck-at faults. Are you sure this is the case?
FPGAs can be low cost too. Another reason to use them is when you need a ton of IO, or my preferred application, real time control systems. In many cases I find it’s easier to get very precise, and predictable, timing…
Looks like the AirPods Pro may address the latency issue. https://gizbuyerguide.com/are-the-airpods-pro-good-for-gamin... “AirPods Pro and Powerbeats Pro that are wirelessly connected to an iOS device, such as an iPhone…
Before you go too far down this path you should look into previous works and understand why they failed. There’s a ton of information out there on this. Here’s something to get you started:…
https://www.folklore.org/StoryView.py?project=Macintosh&stor... "By this point, I was crying harder, and Bob looked like he might start crying at any moment now, too. We were also pretty far from Bandley 4 by now, and…
Is the flowchart system different from a transition system? https://en.wikipedia.org/wiki/Transition_system If not, I don't know of a way to make that machine without some timing assumptions.…
The main issue with the comments are people are mixing terms without knowing it. To many a single instruction executed on a CPU is an atomic event. This is not the case for a circuit designer (and FPGAs are closer to…
Even the most trivial design will need some form of synchronization which implies handshaking of some kind. Asynchronous design is a really interesting field where it's pretty easy to get wins at the circuit level, but…
> The same can be done with asynchronous designs, in more relaxed way. Sure, just ask these guys: https://chronostech.com/technology Chronos Link: A QDI Interconnect for Modern SoCs…
There's a lot of interesting research out there as designers having been toying with asynchronous for decades. For example this one sponsored by Intel where they put an asynchronous instruction length decoder into a…
This implies yield loss is mostly due to small delay defects and not stuck-at faults. Are you sure this is the case?
FPGAs can be low cost too. Another reason to use them is when you need a ton of IO, or my preferred application, real time control systems. In many cases I find it’s easier to get very precise, and predictable, timing…
Looks like the AirPods Pro may address the latency issue. https://gizbuyerguide.com/are-the-airpods-pro-good-for-gamin... “AirPods Pro and Powerbeats Pro that are wirelessly connected to an iOS device, such as an iPhone…
Before you go too far down this path you should look into previous works and understand why they failed. There’s a ton of information out there on this. Here’s something to get you started:…
https://www.folklore.org/StoryView.py?project=Macintosh&stor... "By this point, I was crying harder, and Bob looked like he might start crying at any moment now, too. We were also pretty far from Bandley 4 by now, and…