Oh, I was mistaken. I've verified that at least the rev instruction works (tested on clang -march=rv64imafdcb0p94).
$ cat /proc/cpuinfo processor : 0 hart : 2 isa : rv64imafdc mmu : sv39 uarch : sifive,u74-mc
No. VisionFive2's RISC-V CPU does not have the B extension. I confirmed it on the actual device. $ cat /proc/cpuinfo processor : 0 hart : 2 isa : rv64imafdc mmu : sv39 uarch : sifive,u74-mc
Oh, I was mistaken. I've verified that at least the rev instruction works (tested on clang -march=rv64imafdcb0p94).
$ cat /proc/cpuinfo processor : 0 hart : 2 isa : rv64imafdc mmu : sv39 uarch : sifive,u74-mc
No. VisionFive2's RISC-V CPU does not have the B extension. I confirmed it on the actual device. $ cat /proc/cpuinfo processor : 0 hart : 2 isa : rv64imafdc mmu : sv39 uarch : sifive,u74-mc