Interesting because it's examining not just program size or number of instructions, but the Critical Path Length (the longest path of instructions where each instruction uses the result of the previous one) and the Instruction Level Parallelism (how wide a CPU you need to get the fastest execution time -- i.e. equal to the CPL -- assuming perfect branch prediction).
As such this is an ideal measure, unrelated to current (or near future) real world CPUs.
They also repeat the analysis with a limited window of instructions (4, 16, 64, 200, 500, 1000 and 2000) effectively adding the effects of a limited size ROB (Re-Order Buffer) and limited decode&commit widths (for which they somewhat unrealistically only consider half the ROB size).
> In all cases, the ISAs track each other closely. The largest difference is for CloverLeaf at a window size of 2000, where RISC-V has 12% less ILP available. The only case where RISC-V has more ILP at large window sizes is STREAM with a 5.8% advantage. In every case however, at lower window sizes (500 or less), RISC-V has more ILP available with AArch64 overtaking at higher window sizes.
I don’t really know what to make of this article. On one hand, it’s an interesting study of a theoretical IPC limit on some real codes. On the other hand, I don’t believe authors manage to show what they claim to show:
- it doesn’t seem like they take instruction fusion into account (a common technique used to break frequently occurring serial dependencies)
- the ideal CPU model does not estimate the boundary conditions needed to achieve the same performance with either ISA; the relevant question question is whether simpler RISC-V instructions mean that more decoders/EUs are needed or whether fusion can equalize the difference
>it doesn’t seem like they take instruction fusion into account
It is not mandatory.
Not considering fusion means we are looking at the worst case scenario for RISC-V, that is, a longer-looking path of non-fused yet typically fusable pairs.
Since even then RISC-V is looking no worse than ARM (even slightly better!), this is a very positive result for RISC-V.
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[ 3.6 ms ] story [ 19.0 ms ] threadAs such this is an ideal measure, unrelated to current (or near future) real world CPUs.
They also repeat the analysis with a limited window of instructions (4, 16, 64, 200, 500, 1000 and 2000) effectively adding the effects of a limited size ROB (Re-Order Buffer) and limited decode&commit widths (for which they somewhat unrealistically only consider half the ROB size).
> In all cases, the ISAs track each other closely. The largest difference is for CloverLeaf at a window size of 2000, where RISC-V has 12% less ILP available. The only case where RISC-V has more ILP at large window sizes is STREAM with a 5.8% advantage. In every case however, at lower window sizes (500 or less), RISC-V has more ILP available with AArch64 overtaking at higher window sizes.
- it doesn’t seem like they take instruction fusion into account (a common technique used to break frequently occurring serial dependencies)
- the ideal CPU model does not estimate the boundary conditions needed to achieve the same performance with either ISA; the relevant question question is whether simpler RISC-V instructions mean that more decoders/EUs are needed or whether fusion can equalize the difference
Is this a peer-reviewed publication?
It is not mandatory.
Not considering fusion means we are looking at the worst case scenario for RISC-V, that is, a longer-looking path of non-fused yet typically fusable pairs.
Since even then RISC-V is looking no worse than ARM (even slightly better!), this is a very positive result for RISC-V.
Since only the baseline rva20 (rv64gc) was considered and RISC-V did well (i.e. no worse than ARM) regardless, this is a very positive result.