Hey guys, I've been working for 10+ years in the RISC-V space (mainly AI and Network Packet processing accelerators) and teaching RISC-V computer architecture classes for 6+ years at both grad and undergrad levels. I got my PhD last year and transitioned to industry.
I had a ton of material and recordings (thanks pandemic, I guess) of my lectures and decided to put them up on YouTube. First lecture is here --> https://youtu.be/izPdo7n1u1I
More to follow in the coming days. If you subscribe to the channel, you get notified when new videos are out.
I'm very hands-on in the approach; the idea is to finish the course with an in-order, single-pipeline RV32IM processor running Coremark.
I plan a few bonus lectures on FPGA and ASAP7 synthesis flows, but that depends on how much traction I get on these videos.
2 comments
[ 3.4 ms ] story [ 17.3 ms ] threadI had a ton of material and recordings (thanks pandemic, I guess) of my lectures and decided to put them up on YouTube. First lecture is here --> https://youtu.be/izPdo7n1u1I
More to follow in the coming days. If you subscribe to the channel, you get notified when new videos are out.
I'm very hands-on in the approach; the idea is to finish the course with an in-order, single-pipeline RV32IM processor running Coremark.
I plan a few bonus lectures on FPGA and ASAP7 synthesis flows, but that depends on how much traction I get on these videos.
Love to get your feedback.