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marcux95

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  1. Tiny-Vedas: a generic accelerator interface for RISC-V, from PyTorch op to GDS (github.com)
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  9. My Mental Sanity Script on OpenWRT (gist.github.com)
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  11. ECC SystemVerilog Generator (github.com)
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  14. How to Compile a Large Language Model (LLM) to RISC-V (siliscale.com)
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  19. RISC-V Processor Design – Lec 6 – EXU and Co-Simulation

    Lecture here: https://youtu.be/lI5qD1PkHtA In this lecture, we stitch together a custom Instruction Set Simulator I created with the RISC-V CPU (now with the execution stage) and see the first instructions flowing in…

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  20. RISC-V CPU Design – Lec 5 – Design Top Level and Testbench, Instruction Decode (youtube.com)
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  21. Lecture 4 of how to design a RISC-V Processor available [video] (youtube.com)
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  23. New free course on RISC-V processor design on YouTube (youtube.com)
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