Berkeley Out-of-Order RISC-V Processor (Boom) (2020) (docs.boom-core.org)

The latest version seems to be Sonic Boom:

https://github.com/riscv-boom/riscv-boom

But this project seems to have stagnated with one significant commit in the last year.

If I want to do systems research that needs a simple and synthesizable RISC-V design, what are some good options? BOOM seems to be pretty complicated and I don't really need the out-of-order execution.

I also want to be able to run it on a cheap FPGA, something like Artix A7.

RISC-V is still at the point where open-source implementations (in rtl) are faster than purchasable proprietary ones (in silicon).

XiangShan is currently the fastest open-source CPU implementation: https://github.com/OpenXiangShan/XiangShan

uarch slides: https://tutorial.xiangshan.cc/hpca25/slides/20250302-HPCA25-...

uarch slides with WIP features: https://tutorial.xiangshan.cc/micro25/slides/Microarchitectu...