owww! microsoft github becoming a web app (aka only for the whatng carte web engines), it is impossible to have a 'classic web' look a the repo. Must clone it now... thx microsoft, again.
Only taken a quick skim but this looks like solid material!
RISC-V Vector is definitely tricky to get a handle on, especially if you just read the architecture documentation (which is to be expected really, good specification for an architecture isn't compatible with a useful beginners guide). I found I needed to look at some presentations given by various members of the vector working group to get a good grasp of the principles.
There's been precious little material beyond the specification and some now slightly old slide decks so this is a great contribution.
On a high level, do I understand correctly that SIMD is close to how the hardware works, while Vector Processor is more of an abstraction? The "Strip Mining" part looks like this translation to something SIMD-like. I seems like it's a good abstraction layers, but there is an implicit compilation step right? (making the "assembly" more easily run on different actual hardware)
The example in 1.13 probably would work better if the example with scalar instructions actually had, you know, more instructions than the one with the vector instructions. Otherwise, it's very taxing to read things like "static instruction count and dynamic instruction count both drop dramatically" when your eyes tell you that no, the static instruction count has actually increased.
Also, where does that 38-byte stride even comes from? That number is not even divisible by 4, nevermind by 8!
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[ 3.0 ms ] story [ 27.2 ms ] threadI’d love a similar document for ARM NEON as well.
RISC-V Vector is definitely tricky to get a handle on, especially if you just read the architecture documentation (which is to be expected really, good specification for an architecture isn't compatible with a useful beginners guide). I found I needed to look at some presentations given by various members of the vector working group to get a good grasp of the principles.
There's been precious little material beyond the specification and some now slightly old slide decks so this is a great contribution.
You can implement both regular SIMD ISAs and scalable SIMD/Vector ISAs in a "Vector processor" style and both in a regular SIMD style.
Also, where does that 38-byte stride even comes from? That number is not even divisible by 4, nevermind by 8!
https://blog.timhutt.co.uk/riscv-vector/
It has a visualisation of the element selection stuff at the end.