Around the turn of the millennium I had a Sony Vaio 505TX, which had the same chipset. My machine was running Linux, and I maxed it out to 128MB RAM.
There was a kernel patch for this chipset back then, which treated all memory above the lower 64MB as a RAM disk, which could then be used as swap space.
This prioritized the faster portion of RAM while still having very fast swapping.
Too late to edit - I just saw that the Vaio in fact had the 430TX chipset, not the 430FX. Both were artificially capped at 64MB of fast RAM, as they were late Pentium chipsets, and Intel rather wanted to sell the then-new Pentium II chips and chipsets if you wanted to have more memory.
In the modern era we'd probably repurpose NUMA support if this issue came up again, so that tasks would prioritize the fast portion of memory but the remainder would be fully usable as RAM (with fewer of the extra copies you'd have from "swap" use).
It is funny to see how these older machines perform at their higher end limits. I'm guessing the idea on this was that if you needed that much RAM, the sacrifice of L2 cache was a worth while trade off.
It was only a few weeks ago that I found out the original BeBOX computers would switch off L2 cache when running in dual CPU mode. It was just a limitation of the memory controller. Again, the thinking of, if you need the extra compute over memory bus it would be a worth while trade off.
Looks like the BeBox motherboard didn't have the external L2 in the first place.
Besides web sources, logic dictates this as well: Since dual-cpu was its selling point, it wouldn't make sense to ship a disabled L2 implementaton on the mobo at extra cost. There was no single-cpu model.
> I'm guessing the idea on this was that if you needed that much RAM, the sacrifice of L2 cache was a worth while trade off.
The idea was that nobody in their right mind would at the time populate that particular consumer motherboard/chipset with hundreds of megabytes of RAM because it would be hilariously expensive. If you needed that kind of RAM, you were purchasing a much more expensive workstation anyhow.
By the time 384MB was a merely expensive amount of RAM, nobody would be interested in installing it in a Pentium. Those were the days when Moore's Law was still a very big deal. For that reason the firmware probably never received an update to fix the problem, even if that were possible.
The docs on that motherboard sort of suggest that the motherboard could cache up to 512MB. This motherboard uses the new pipelined burst cache technology with 512K size and the memory cacheable size from 64MB to
512MB. I can't imagine they ever actually tested that.
This would have also still been true even roughly a decade later, during which time the industry was going through a transition from 32-bit computing to 64-bit, and large amounts of RAM read from BIOS in pre-UEFI systems were slower to boot the more memory you had!
Imagine young would-become engineers at the time finding that adding that second stick to their laptop did in fact, not make their systems magically faster.
how funny is this, we used to spend weeks fitting assets into 4MB, and now we spend weeks trying to figure out why a 'Hello World' microservice is OOM-ing in a container with 2GB.
We traded the 'Mo RAM' for 'Mo Layers,' and in the process, we lost the ability to reason about what the hardware is actually doing. Sanglard’s breakdowns are always a sobering cold shower for those of us pampered by modern GC and JITs
Reminds me a bit about installing one of my 128MB 72 pin SIMM modules in a 486, it has the same caching issues. Most board will not accept them anyway (I have both FP and Edo ones) but if you put a lower capacity one in the first slot they will happily boot and accept the full ram amount if all lanes are occupied (which is not a given on all 486 motherboards). Also remember to enable quick ram check or you will be getting more coffee.
Does the language in this not make sense to anyone? Is it trying to say the the L2 cache provided by the chipset is not able to access memory past a specific address?
This reminds me that on an Amiga 600 or 1200, if you add more than 4 (IIRC?) megabytes of RAM through usual means, the PCMCIA slot becomes unusable due to addressing conflicts.
There are workarounds, of course. For instance, the A1208 expansion has a jumper that limits added memory from 8MB to 4MB explicitly so that PCMCIA can be used.
Also, internal CPU caches grow over time - in 286 and before, just was not any cache; in 386 first included page cache for mmu - stores tables with mostly used pages; in next generations sometimes advertised grow of page cache.
So yes, even when your cpu could address similar size of ram, possible it don't have enough page cache for your application.
It sounds like a problem related to memory interleaving. He doesn't say whether the memory modules are identical, my bet is that they differ. Could also be a poor performing motherboard.
More RAM running slower is still true today. With AM5 you probably cannot enable EXPO with four ram slots filled vs two. The gap is not that extreme though.
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[ 3.8 ms ] story [ 38.8 ms ] threadThere was a kernel patch for this chipset back then, which treated all memory above the lower 64MB as a RAM disk, which could then be used as swap space.
This prioritized the faster portion of RAM while still having very fast swapping.
It was only a few weeks ago that I found out the original BeBOX computers would switch off L2 cache when running in dual CPU mode. It was just a limitation of the memory controller. Again, the thinking of, if you need the extra compute over memory bus it would be a worth while trade off.
Besides web sources, logic dictates this as well: Since dual-cpu was its selling point, it wouldn't make sense to ship a disabled L2 implementaton on the mobo at extra cost. There was no single-cpu model.
The idea was that nobody in their right mind would at the time populate that particular consumer motherboard/chipset with hundreds of megabytes of RAM because it would be hilariously expensive. If you needed that kind of RAM, you were purchasing a much more expensive workstation anyhow.
By the time 384MB was a merely expensive amount of RAM, nobody would be interested in installing it in a Pentium. Those were the days when Moore's Law was still a very big deal. For that reason the firmware probably never received an update to fix the problem, even if that were possible.
The docs on that motherboard sort of suggest that the motherboard could cache up to 512MB. This motherboard uses the new pipelined burst cache technology with 512K size and the memory cacheable size from 64MB to 512MB. I can't imagine they ever actually tested that.
Imagine young would-become engineers at the time finding that adding that second stick to their laptop did in fact, not make their systems magically faster.
We traded the 'Mo RAM' for 'Mo Layers,' and in the process, we lost the ability to reason about what the hardware is actually doing. Sanglard’s breakdowns are always a sobering cold shower for those of us pampered by modern GC and JITs
There are workarounds, of course. For instance, the A1208 expansion has a jumper that limits added memory from 8MB to 4MB explicitly so that PCMCIA can be used.
So yes, even when your cpu could address similar size of ram, possible it don't have enough page cache for your application.
https://www.corsair.com/us/en/explorer/diy-builder/memory/2-...