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That sounds like a fun challenge. Feels a lot more tractable than the neural net one.
Is there something like an Extract-SPICE tool that takes a circuit and gives you back a text rendering of it ?
people who can do this stuff are super-smartypants

but reminds me how we're going to find out on an industrial level when the Saudis give China some nvidia chips they were grifted

they've cloned lots of chips before but nothing that advanced

At my uni, 15 years ago, one postdoc reverse engineered NVIDIA chip and wrote more performant compiler. He did that by connecting oscyloscops to all chip's outputs and started with applying random current on inputs. Using ML and his genius he rediscoverd all opcodes including a few hidden ones. Eventually he got hired by some company that was doing a lot of GPU on supercomputers.
Detailed write-up please, or it didn't happen. At least not as described.

Really simple ICs with a few counters etc in there might be possible to RE this way. Complex ICs with lots of internal state, memory blocks etc like a modern-ish GPU? Not a chance.

Some hybrid approach? Software fiddling with the chip's internals, with say. a big FPGA attached to physically probe outputs? Architecture docs, and maybe some IC die shots at hand? Perhaps (hence my ask for "detailed").

Sounds like requiring the kind of hardware setup that would not be available to uni students.

I thought the article was going to be about how people scan chips

Rapid Chip Reverse Engineering Using Laser, Focused ion beams, and Scanning electron microscope https://academic.oup.com/mam/article/30/Supplement_1/ozae044...

FIBs are also used to test modifications before doing a respin. I'm still in awe that matter can be manipulated so precisely

FIB is awesome but there’s nothing easy about it, and the success rates are not super great.
30 minutes with /goal for the solution from Sol w/ high.
Getting a logic-gate-level netlist from a GDS is trivial with industry standard chip design tools. Circuit designers do this every day. The hardest part will be reverse engineering the functionality.

I wish I had more time and I'd throw Calibre at it.

No need for Calibre. Me + KLayout + Claude had a verilog sim of the example vcd input and gate-level netlist 30 minutes after I cloned the repo.
What prerequisites I need to solve this puzzle? I don't have much knowledge in electrical engineering.
I encourage you to try, but honestly, with almore 30 years experience making chips, I would still classify this puzzle as "pretty damn hard".
I've looked at Visual 6502 and it's way beyond me. I've even looked at the scans where it shows how they severed the connection to disable 6502 decimal mode on the NES.
Hasn’t Ken Shirriff been doing this for quite a while? (:->
Man, these guys always have insane puzzles. What the heck.
I reverse engineered the Game Boy from pictures of the die - https://github.com/aappleby/metroboy - so yes, it's totally doable. It is also incredibly tedious and frustrating.

Not sure if that gives me an advantage in this challenge, but I have too many things to do already. :D

Earlier this year I watched a video from a conference where a researcher took a die shot (one of Ken's I think) and then did guided learning by identifying on the image which were the different layers, metals, and layout of the gates on the die. The machine learning algorithm could go off and identify other gates and provide a netlist(?).

I've tried searching REverse, and some of the hacker conferences from January, but haven't found it yet.

seeing this was done 5yrs ago. Is this easily recreatable by an AI model nowadays? If so, what does it make you feel?
(A crash course in how chips get made)

That paragraph + illustration is one of the simplest, concise, easy-to-grasp descriptions of IC design process I've come across. Nice!

Now the reverse: what I'd really love is a free (libre) automated toolset to go from IC die shot(s) -> transistors+interconnects -> gate-level schematic (logic gates & flipflops). Person interested in RE a chip's function can take it from there.

To me, the whole "here's a section of the die photo" to "that's an n-bit adder" etc step is like black magic. Not to mention extremely tedious.

Get that to a higher-level view easy, and it would be much more doable to work out function of each element.

Solved it. Took me ~6 human hours, over a total of 24 hours. But it was NOT easy!

I've been making chips for amost 30 years, and I run the https://github.com/smprather/engineering-loadout project, so I had all the tools sitting at my fingertips (KLayout, Surfer, Icarus Verilog, etc).

Pretty same tool used to me.