I encourage you to try, but honestly, with almore 30 years experience making chips, I would still classify this puzzle as "pretty damn hard".
That would have added a definite layer of complexity, but really just a token/cpu drain on the puzzle solver. Had they done that, I would have had Claude write a "gds matcher" that took the gds files of the sky std-cell…
The Last Starfighter :).
Nope. I work at Cadence and literally have free access to every one of our tools, but I didn't use a single one of them to solve the puzzle.
No need for Calibre. Me + KLayout + Claude had a verilog sim of the example vcd input and gate-level netlist 30 minutes after I cloned the repo.
Solved it. Took me ~6 human hours, over a total of 24 hours. But it was NOT easy! I've been making chips for amost 30 years, and I run the https://github.com/smprather/engineering-loadout project, so I had all the tools…
I clicked link expecting the likes of Defender and Joust. Nope.
I'm not even a "car guy" but I sure would love to have one of those GT40's from Ford vs. Ferrari. (With a working door :))
They now have a mostly functional interpreter. This should turbo-charge tight write/test/write/test loops. I wish I would have had it when I wrote my last mid-sized Crystal project.
You wrote an event driven simulator. We use Verilog simulators in my industry. http://iverilog.icarus.com/
Looks like some people are trying to re-create it at least. https://github.com/srg320/FpgaSnes
Has Nintendo released officially, or leaked, the RTL for any of the processors in the SNES? If someone could get their hands on that, then the emulation authors should be able to achieve perfection.
I encourage you to try, but honestly, with almore 30 years experience making chips, I would still classify this puzzle as "pretty damn hard".
That would have added a definite layer of complexity, but really just a token/cpu drain on the puzzle solver. Had they done that, I would have had Claude write a "gds matcher" that took the gds files of the sky std-cell…
The Last Starfighter :).
Nope. I work at Cadence and literally have free access to every one of our tools, but I didn't use a single one of them to solve the puzzle.
No need for Calibre. Me + KLayout + Claude had a verilog sim of the example vcd input and gate-level netlist 30 minutes after I cloned the repo.
Solved it. Took me ~6 human hours, over a total of 24 hours. But it was NOT easy! I've been making chips for amost 30 years, and I run the https://github.com/smprather/engineering-loadout project, so I had all the tools…
I clicked link expecting the likes of Defender and Joust. Nope.
I'm not even a "car guy" but I sure would love to have one of those GT40's from Ford vs. Ferrari. (With a working door :))
They now have a mostly functional interpreter. This should turbo-charge tight write/test/write/test loops. I wish I would have had it when I wrote my last mid-sized Crystal project.
You wrote an event driven simulator. We use Verilog simulators in my industry. http://iverilog.icarus.com/
Looks like some people are trying to re-create it at least. https://github.com/srg320/FpgaSnes
Has Nintendo released officially, or leaked, the RTL for any of the processors in the SNES? If someone could get their hands on that, then the emulation authors should be able to achieve perfection.