Shouldn't that have already been do-able? I know the The MOnSter 6502 is a thing. The 386 I have no idea about though, that's to far out of my wheel house.
A replica 386 would be impractically large - it's got around 275k transistors, compared to the 3.5k in the 6502. At the same scale as the MOnSter 6502, that'd be about a hundred square feet of PCB.
The number of layers isn't even remotely close to being a constraint. The real i386DX was manufactured on a process which only supported two metal layers, and a PCB version isn't subject to the same constraints as silicon.
Components like transistors usually have to go on the surface of a PCB. (While there are techniques for embedding components in a PCB, they're extraordinarily expensive and would not be feasible for a project like this one.)
Probably not, because transistors produce some heat, and you can't really sandwich surface mount transistors between PCB layers either. You could vertically stack PCBs with some spacing, however, but then normal PCBs will do the job.
It is possible to embed components in the middle of a pcb, but it's a pretty specialist process (read: a pain in the neck because it interleaves the pcb fabrication and assembly stages, making both steps more complicated).
The ARM1 was a 32-bit CPU and it only had about 25K transistors so that one might be fair game if you can bring the components a little bit closer together, but you don't need a fancy PCB for that, and I guess the clock speed would need to be very slow if it's several square feet in size.
The layers still need something to link together. You could try a board with as many MSPM0C1104 as you can fit on each side. I'm sure you could use the layers to make some esoteric interconnection map.
The number of levels of traces and gates laid out is an important aspect of how much sophistication and capability available to connect ICs on a pcb. You are laying out power and ground and communication. There are lots of other considerations like the complexity of what you can plan to layout using software. But you stack layers of traces to add capability. More layers is naively more capability.
> TOKYO, April 25, 2025 -- OKI Circuit Technology... OTC is seeking to establish mass production technology by October 2025 at its Joetsu Plant in Joetsu City, Niigata Prefecture
Dan, this is 2025! Not a Hacker News-worthy at the end of 2026.
Also, 124 layer PCB is ONLY 15% extra than the conventional 108 layer PCB. Incremental upgrade!
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The number of layers isn't even remotely close to being a constraint. The real i386DX was manufactured on a process which only supported two metal layers, and a PCB version isn't subject to the same constraints as silicon.
Higher density chip packing is only one advantage. Unlikely going to see such things in cost-optimized consumer products. =3
This article from Aug 2026 says 20 layers are for complex designs. https://www.pcbasic.com/blog/pcb-layers.html. So 124 layers looks like a huge increase.
Not my area, probably got it all wrong, hope this is useful.
Dan, this is 2025! Not a Hacker News-worthy at the end of 2026.
Also, 124 layer PCB is ONLY 15% extra than the conventional 108 layer PCB. Incremental upgrade!