One thing I wonder about is that these CPUs are just so much faster than their memory controllers. So why not add more? Why don't they have a memory controller per core, for example?
I think it mostly is for more controllers to be useful that means more PHYs and more actual pins on the package and more traces on the board and more sockets for the memory and... The space and cost of all of that is substantial (to a point, and then it just physically can't be manufactured).
Cost, and especially now, cost of memory! But you can buy AMD chips with 2 controllers (consumer), 4 (threadripper), 6 (8005), 12 (EPYC) memory channels, so in effect you can. Next generation Zen 6 Epyc has 16 channels. Roughly you get about 1 channel per chiplet, but you csn adjust if you need more memory bandwidth by buying fewer chiplets, eg there is an 8 core EPYC if you want to optimisise for bandwidth. But many applications are not bandwidth bound so this isn't the right choice, eg they are IO bound, rarely compute bound.
It's not always trivial to saturate available memory bandwidth. You may need to use more than one cpu, or the overall topology of the chip you're working with. For example, what if the L3 cache is actually split in two [0]? In such cases, adding more bandwidth doesn't do much for you.
I was going to be sad than Zen 6c was divergent, but they increased a bunch of OoO structures on Zen 6c? To absorb more potential latency, since the memory is going to be heavier loaded? Ok, that I can appreciate!
It's absolutely wild that adjusting some l3 and using a smaller node goes from 12 to 32 cores for basically the same chip.
I wonder if the CCD will remain as monolithic as it does, for how long? The l3 latency being signficantly higher for 6c (10.3ns zen5 -> 10.7ns z6 -> 16.4ns z6c) feels like a symptom of a broader scaling challenge as the CCD hosts more and more. I can imagine dividing zen 7 or zen8 CCD into partitions, perhaps?
I think it's less there because of differences in the memory subsystem, but more because clock targets are lower so they can afford more. The structures they grew cost basically nothing in die area, but make timing tighter. It's possible they'd like them to be bigger for the non-c core too, but can't fit them in their timing constraints.
The unified L3 per CCD really helps on some key desktop loads (especially games). Most server throughput loads partition nicely into smaller partitions, but most games are hurt so bad by the latency penalty of crossing into a different partition that AMD's game drivers park the second CCD on their 2-CCD CPUs when they detect a game running. So long as games are an important target for them, I suspect they will not partition the CCD again. (It, of course, used to be parititioned for Zen 1 and 2.)
The instruction level parallelism in the 2-ahead branch prediction is super cool stuff, I know zen5 had this feature but it's kind of crazy that memory is so slow relative to the cores that this complexity is beneficial and worthwhile.
It is hilarious that the SPEC2026 graph does not include apple's P-cores. And no, not because they are ARM and not x86, since Graviton is included. It is because their integer & FP scores of 9.8 & 13 respectively absolutely wipe out everything else on this chart.
Regular Ryzen parts are still reasonably relevant for server use! They support ECC, so there's nothing immediately disqualifying them - see the rebranded "EPYC" 4005 series, for example.
A company like Hetzner isn't going to care an awful lot whether they deploy one big SP5 server or four small AM5 ones for the VM instances they rent out: the only thing that matters is TCO per performance.
Want to stick four NVMe SSDs, a 25Gbit NIC, 256GB of ECC RAM, and some OOB module on a Ryzen board? No problem whatsoever. Want to do the same with an Apple CPU? Ehhh, that's going to be slightly more challenging...
The single-threaded results of the Apple cores are excellent, but the multi-threaded results per socket of a Zen 6 absolutely wipe out any Apple CPU.
The Apple CPUs may be great for a personal computer, but they are not competitive with a server CPU.
Moreover, the SPEC floating-point results are not really representative for the floating-point performance of Zen 5 and Zen 6 that can be reached with optimized AVX-512 programs, which is much greater.
What looks like a lot of small balanced improvements to the core itself. Four vector loads per cycle at 256b of less, I wonder if the gather performance is finally acceptable?
The real star looks like the c cores though. 32 C cores per chiplet with increased l3 cache is impressive
> AMD has reduced the number of integer multiply units from three to two, with PDEP and PEXT throughput also falling from three instructions per cycle to two.
Are PDEP and PEXT using the same (parts of) circuits as multiply (they are very different operations...), or are this just two independent drops of circuitry and the wording is just a bit unclear?
They are unlikely to share circuits with the multipliers, but the 2 of the 6 execution units that include multipliers must be identical, to simplify layout, and the PDEP/PEXT circuits are allocated to these 2 units, like the multipliers.
32 cores is a lot of cores on a CCD. Is there a there any smaller logical unit between a CCD and a core, or are you expected to wrangle 32 cores in your lowest NUMA level?
This is amusing since Intel seems to be sort of going in the other direction lately: their efficiency cores are becoming more like their performance cores with each new generation (at least in so far as they are getting wider and more capable of higher clock speeds), and there even seem to be some rumors that the two design trains may get "merged" in the future.
The worst thing about consumer (AM5) Zen4 and Zen5 is the I/O die chiplet and memory controller on it. I've heard they're finally going to ship a new I/O chiplet in Zen6 on a much smaller node. Their AM5 memory controller when using both memory channels is terrible. Extremely hard or impossible to get above 3600 MT/s.
Of all the things I'm looking forward to on Zen6, an improved memory controller is at the top of the list.
Edit: and yes, others may say the paltry few PCIE 5.0 lanes is the worst thing about AM5, but that doesn't affect my usage much, and unfortunately I think that's a limitation of AM5 itself rather than the I/O chiplet.
Agreed, this is likely going to change the landscape for people ekeing everything out of an AMD-based HEDT.
To take full advantage of it, folks likely will want A) a new motherboard with likely a new chipset to support the higher frequencies and B) <GULP> higher frequency DDR5.
I’d love more memory bandwidth with the limited 2-channels I have, but the 2x48GB (96GB) of “tuner memory” I bought in February 2025 I’m not even sure is manufactured anymore. I paid $440 back then, and my understanding is it’s not produced now, and commands $2500 - $3000 on the second-hand market.
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[ 2.4 ms ] story [ 16.8 ms ] thread[0] https://en.algorithmica.org/hpc/cpu-cache/sharing/#saturatin...
It's absolutely wild that adjusting some l3 and using a smaller node goes from 12 to 32 cores for basically the same chip.
I wonder if the CCD will remain as monolithic as it does, for how long? The l3 latency being signficantly higher for 6c (10.3ns zen5 -> 10.7ns z6 -> 16.4ns z6c) feels like a symptom of a broader scaling challenge as the CCD hosts more and more. I can imagine dividing zen 7 or zen8 CCD into partitions, perhaps?
The unified L3 per CCD really helps on some key desktop loads (especially games). Most server throughput loads partition nicely into smaller partitions, but most games are hurt so bad by the latency penalty of crossing into a different partition that AMD's game drivers park the second CCD on their 2-CCD CPUs when they detect a game running. So long as games are an important target for them, I suspect they will not partition the CCD again. (It, of course, used to be parititioned for Zen 1 and 2.)
Different story when you're talking about the context of a desktop or mobile.
2. What flags & compiler?
3. Can't run Linux on that M5/M6 can we?
A company like Hetzner isn't going to care an awful lot whether they deploy one big SP5 server or four small AM5 ones for the VM instances they rent out: the only thing that matters is TCO per performance.
Want to stick four NVMe SSDs, a 25Gbit NIC, 256GB of ECC RAM, and some OOB module on a Ryzen board? No problem whatsoever. Want to do the same with an Apple CPU? Ehhh, that's going to be slightly more challenging...
The Apple CPUs may be great for a personal computer, but they are not competitive with a server CPU.
Moreover, the SPEC floating-point results are not really representative for the floating-point performance of Zen 5 and Zen 6 that can be reached with optimized AVX-512 programs, which is much greater.
The real star looks like the c cores though. 32 C cores per chiplet with increased l3 cache is impressive
Are PDEP and PEXT using the same (parts of) circuits as multiply (they are very different operations...), or are this just two independent drops of circuitry and the wording is just a bit unclear?
Of all the things I'm looking forward to on Zen6, an improved memory controller is at the top of the list.
Edit: and yes, others may say the paltry few PCIE 5.0 lanes is the worst thing about AM5, but that doesn't affect my usage much, and unfortunately I think that's a limitation of AM5 itself rather than the I/O chiplet.
To take full advantage of it, folks likely will want A) a new motherboard with likely a new chipset to support the higher frequencies and B) <GULP> higher frequency DDR5.
I’d love more memory bandwidth with the limited 2-channels I have, but the 2x48GB (96GB) of “tuner memory” I bought in February 2025 I’m not even sure is manufactured anymore. I paid $440 back then, and my understanding is it’s not produced now, and commands $2500 - $3000 on the second-hand market.