A bit of clickbait. Brief explanation of why that huge perf gap on a well-solved problem: 1. The `memcpy` idea is trivial. I know it's there to serve a different argument. But saying "professional" can't think of…
This page has some interesting ideas about "safety" without any pre-conditions. As a starter, Java is safe. Probably safer than most of the C-based candidates on this list. And we are only speaking about Java without…
The open-sourced toolchain of RISC-V accepts any kind of extensions as long as they are in the reserved code space, basically out-of-the-box. The current ratifying body does not hold any special toolchain or legal…
My Gosh, what was happening with this project? At first they target to ship in chrome 97, then 101, then 105, then 109, now 113. Are we building fusion reactors that are constantly four months away?
Well this is bad. Just checked the code, `RandomState` invokes `wasi::random_get()` on wasi target. It means virtually every std program in Rust would require random number generator privilege in the upcoming WASI…
This article turned up with a valuable proposition. Although I would still argue open source software itself is as political as it can get (Forked code has no value. Communities of people behind the code matters), but I…
RISC no longer has the clear border as it had 30 years ago. Nowadays RISC just means an ISA has most of the following points: 1. Load/Store architecture 2. Fixed-length instructions or few length variations. 3. Highly…
Finally some updates after all these years. I'm just curious about the relations between the older "nanoprocess" and the now Component Model. Previously the nanoprocess model promised fine-grained containerization, I…
On ISA design, it is just so wrong to endorse the opinion of a single person. ISA design has three significant parties of interest: IC designers, compiler authors, and software developers. No one can master these three…
Chip and ISA are almost irrelevant stuff. No matter how you emphasize on end product performance, you cannot deny there SHOULD be a metric to compare ISA designs.
From my perspective, Rust does not belong in kernel. But meanwhile Linux kernel does not belong in modern infrastructure. Until the day a mature kernel-oriented language and an established kernel showed themselves,…
They seem to adopt a rapid iteration model closer to browser rather than typical language runtimes. So a browser 1.0 is nothing close to finished. I personally have no problem on it. But I think it is indeed strange…
Just curious, how would a high-level IR processor knows beforehand that a certain piece of code was longer/shorter than 4kB/1MB, if it do not try to compile it in pieces first.
Mainly because they can. They already have excellent team & experience in designing low power cores from the ground up, and also they have their great LLVM team for the compiler. Core plus compiler, that's all you need…
Hasn't looked into this. But definitely curious about the relationship between the two https://news.ycombinator.com/item?id=29217829
Alongside with Windows long since 1.35 https://github.com/rust-lang/rust/pull/20367
For those who are wondering why the heck would a microarhitectural exploit would "work" on a ISA level as the title suggested: No, it doesn't. This paper talks only about textbook RISC-V BOOM cores. Interesting work,…
I've been tracking this since May. I'd say it's disappointing that it did not make itself into 1.62 in the end.
This sounds suspiciously like using risc-v for web-assembly businesses. Any advantage for this method vs non-JIT wasm? (perfromance or platform compatibility?)
I would say the current state of RISC-V is complete but still lacks the final kick. Yes, you can now build an application core out of it, given that V, B, K extensions are now ratified under RVA22. However most…
Then write up an actually meaningful array processing function and translate it into asm is even less rocket science. The author starts with a apparently meaningless `int x = a[i];`, but did not ask an obvious question…
Yes it is negligible. The problem is that indexed load/store is a non-issue. There are ready-to-use simulation data that shows indexed load/store has minimal impact on dynamic code size.If someone uses an overkill…
Yes, the author's defence for Myth #1 does not strike me as a correct defence from the RISC-V perspective. Going to compressed instruction and compressed macro-op fusion is way overkill for the very basic indexed…
There is also the problem of binary layout. RPC values on binary size, and IPC values on latency with zero ser/des. The two binary layouts are simply incompatible. You can do zero copy with RPC, but that does not help…
Sync and async are all about cooperatively yielding control flow. However, in many cases, you may want to yield control on IPC, or to hold onto control on RPC. Yielding control depends on the sender logic. IPC/RPC…
A bit of clickbait. Brief explanation of why that huge perf gap on a well-solved problem: 1. The `memcpy` idea is trivial. I know it's there to serve a different argument. But saying "professional" can't think of…
This page has some interesting ideas about "safety" without any pre-conditions. As a starter, Java is safe. Probably safer than most of the C-based candidates on this list. And we are only speaking about Java without…
The open-sourced toolchain of RISC-V accepts any kind of extensions as long as they are in the reserved code space, basically out-of-the-box. The current ratifying body does not hold any special toolchain or legal…
My Gosh, what was happening with this project? At first they target to ship in chrome 97, then 101, then 105, then 109, now 113. Are we building fusion reactors that are constantly four months away?
Well this is bad. Just checked the code, `RandomState` invokes `wasi::random_get()` on wasi target. It means virtually every std program in Rust would require random number generator privilege in the upcoming WASI…
This article turned up with a valuable proposition. Although I would still argue open source software itself is as political as it can get (Forked code has no value. Communities of people behind the code matters), but I…
RISC no longer has the clear border as it had 30 years ago. Nowadays RISC just means an ISA has most of the following points: 1. Load/Store architecture 2. Fixed-length instructions or few length variations. 3. Highly…
Finally some updates after all these years. I'm just curious about the relations between the older "nanoprocess" and the now Component Model. Previously the nanoprocess model promised fine-grained containerization, I…
On ISA design, it is just so wrong to endorse the opinion of a single person. ISA design has three significant parties of interest: IC designers, compiler authors, and software developers. No one can master these three…
Chip and ISA are almost irrelevant stuff. No matter how you emphasize on end product performance, you cannot deny there SHOULD be a metric to compare ISA designs.
From my perspective, Rust does not belong in kernel. But meanwhile Linux kernel does not belong in modern infrastructure. Until the day a mature kernel-oriented language and an established kernel showed themselves,…
They seem to adopt a rapid iteration model closer to browser rather than typical language runtimes. So a browser 1.0 is nothing close to finished. I personally have no problem on it. But I think it is indeed strange…
Just curious, how would a high-level IR processor knows beforehand that a certain piece of code was longer/shorter than 4kB/1MB, if it do not try to compile it in pieces first.
Mainly because they can. They already have excellent team & experience in designing low power cores from the ground up, and also they have their great LLVM team for the compiler. Core plus compiler, that's all you need…
Hasn't looked into this. But definitely curious about the relationship between the two https://news.ycombinator.com/item?id=29217829
Alongside with Windows long since 1.35 https://github.com/rust-lang/rust/pull/20367
For those who are wondering why the heck would a microarhitectural exploit would "work" on a ISA level as the title suggested: No, it doesn't. This paper talks only about textbook RISC-V BOOM cores. Interesting work,…
I've been tracking this since May. I'd say it's disappointing that it did not make itself into 1.62 in the end.
This sounds suspiciously like using risc-v for web-assembly businesses. Any advantage for this method vs non-JIT wasm? (perfromance or platform compatibility?)
I would say the current state of RISC-V is complete but still lacks the final kick. Yes, you can now build an application core out of it, given that V, B, K extensions are now ratified under RVA22. However most…
Then write up an actually meaningful array processing function and translate it into asm is even less rocket science. The author starts with a apparently meaningless `int x = a[i];`, but did not ask an obvious question…
Yes it is negligible. The problem is that indexed load/store is a non-issue. There are ready-to-use simulation data that shows indexed load/store has minimal impact on dynamic code size.If someone uses an overkill…
Yes, the author's defence for Myth #1 does not strike me as a correct defence from the RISC-V perspective. Going to compressed instruction and compressed macro-op fusion is way overkill for the very basic indexed…
There is also the problem of binary layout. RPC values on binary size, and IPC values on latency with zero ser/des. The two binary layouts are simply incompatible. You can do zero copy with RPC, but that does not help…
Sync and async are all about cooperatively yielding control flow. However, in many cases, you may want to yield control on IPC, or to hold onto control on RPC. Yielding control depends on the sender logic. IPC/RPC…