The article doesn't sell it well. Basically, its fundamentally more expensive... But lol, where else are you gonna go for your reticle size chips?
Its more power efficient than GDDRX, but not necessarily far from LPDDRX.
As a they speculated, a compromise seems like the future. Like a wider memory standard with stricter trace requirements, but not wide enough to require an interposer + control chip.
Or maybe just external memory controller/cache chips like the 7900 XTX, where the chip space for all the pins is less of a concern.
Not necessarily. There are different kinds if multi chip interconnects (with the fabs introducing more and more over the years), and leaving out HBM potentially allows for a cheaper interconnect over a smaller area.
HBM is getting more expensive AND we've hit the SRAM density scaling limits AND current GPU lines shipments delays are expected to last until Q2 of next year so no price relief anytime soon. Ouch.
I would be very surprised if AMD isn't looking into "HBM-lite", i.e. same 2.5D structure, but instead of the parallel HBM interface, using a serial IF/GMI interface (fewer pins, higher frequency), so that you can mount it on a much cheaper organic (PCB) interposer.
I'm not really sure I believe anything they say... I had one of those early Pentium 4s with RIMM memory, and it was one of the hottest and slowest memory I have ever worked with. DDR4/5 seems to work for me just fine.
The infamous vapourware Glaze3D from Bitboys (ex-demosceners!) didn't even ship, and yet we now have tile based rendering in all GPUs because of how that technology first went to mobile by way of Qualcomm, and then desktop GPUs.
What I'm saying is, truly fundamental tech has a way of surviving bad companies / business decisions, eventually; as the article points out, they use HBM because they have to.
> The infamous vapourware Glaze3D from Bitboys (ex-demosceners!)
I still remember the grandiose claims of Glaze 3D and its 16 or 32MB of EDRAM. I can even recall the HDR renderings of those dusty wild west town scenes from the demo in the PC Gamer article and other media outlets. They did receive funding but I don't think hardware was ever tapped out or prototyped and all the renderings were software.
Perhaps I'm wrong... but as far as I can see, no RAM technology currently allows variable latency?
Ie. the host says "I want data from this address", and the RAM can reply 2 clock cycles later with "Here is that data you asked for" or "I'm still getting that data for you, just wait a few more clock cycles please".
Such schemes allow the RAM manufacturer to implement error detection/correction/remapping, which would allow them to push their designs far closer to what physics allows. (you can make something much much smaller/faster if you only need it to work 99% of the time, and use a fallback path/mechanism for the remaining 1%)
Wouldn't it be cheaper to integrate DDR chiplets in the package, like Apple is doing? Even though the approach is not competitive with HBM in performance, on Apple processors it does seem to offer better power efficiency and bandwidth compared to off-package memory. But for some reason neither Intel nor AMD are moving in that direction.
I wish the author would have put some actual numbers on the cost of the different technologies.
Arguing about tradeoffs including that information would be much more meaningful.
Tangential question: is Oxide using HBM in their racks? My understanding is that part of their value proposition is making hardware tech that's usually built for the hyperscalers available to on-prem datacenters; this seems like the kind of technology they might be referring to.
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[ 0.21 ms ] story [ 35.5 ms ] threadIts more power efficient than GDDRX, but not necessarily far from LPDDRX.
As a they speculated, a compromise seems like the future. Like a wider memory standard with stricter trace requirements, but not wide enough to require an interposer + control chip.
Or maybe just external memory controller/cache chips like the 7900 XTX, where the chip space for all the pins is less of a concern.
> Rambus
I'm not really sure I believe anything they say... I had one of those early Pentium 4s with RIMM memory, and it was one of the hottest and slowest memory I have ever worked with. DDR4/5 seems to work for me just fine.
What I'm saying is, truly fundamental tech has a way of surviving bad companies / business decisions, eventually; as the article points out, they use HBM because they have to.
I still remember the grandiose claims of Glaze 3D and its 16 or 32MB of EDRAM. I can even recall the HDR renderings of those dusty wild west town scenes from the demo in the PC Gamer article and other media outlets. They did receive funding but I don't think hardware was ever tapped out or prototyped and all the renderings were software.
https://web.archive.org/web/20010118210900/http://www.bitboy...
Ie. the host says "I want data from this address", and the RAM can reply 2 clock cycles later with "Here is that data you asked for" or "I'm still getting that data for you, just wait a few more clock cycles please".
Such schemes allow the RAM manufacturer to implement error detection/correction/remapping, which would allow them to push their designs far closer to what physics allows. (you can make something much much smaller/faster if you only need it to work 99% of the time, and use a fallback path/mechanism for the remaining 1%)
Fairly sure HBM3 implements all of this.
HBM2 might also have hard (fuse-based) remapping, not sure.